Hardware Trojans Detection Using GNN in RTL Designs” was published by researchers at University of Connecticut and University ...

For many aspects of an EDA flow, hallucinations from AI are not really that serious, because that is no worse than engineers on a Friday afternoon.

Analog and mixed signal content is adding risk to ASIC designs. Pessimists see the problem getting worse, while optimists point to AI and chiplets for relief.

Disaggregration requires traffic cops and in-chip monitors to function as expected over time. The shift from SoCs to multi-die assemblies requires more and smarter controllers to be distributed ...

Ensuring trusted execution across multiple chiplets and vendors is more complex than in traditional monolithic SoCs.

New tools and techniques are being developed and can help keep the verification process secure, alongside a firm foundation of good design verification practices.

An Agentic Approach for SoC Security Verification using Large Language Models” was published by researchers at University of ...

D-IC trends and challenges; virtual prototypes for SDVs; chiplet security; sustainable AI development; quality best practices ...

Creating high-quality and high-performance autonomous and connected vehicles while mitigating safety risks across their ...

A new technical paper titled “Exploring optimal TMDC multi-channel GAA-FET architectures at sub-1nm nodes” was published by ...

Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration” was published by researchers at Yokohama National University, ...

A new technical paper titled “Practical Guidance on Selecting Analytical Methods for PFAS in Semiconductor Manufacturing ...